The present invention relates to a semiconductor integrated circuit having a plurality of thin film transistors (TFT) and more particularly to a monolithic active matrix circuit having an active matrix circuit and a logic circuit (called also as a peripheral circuit) for driving it on one and the same substrate and to a fabrication method thereof. The semiconductor integrated circuit fabricated by the present invention may be formed either on an insulating substrate such as glass and on an insulating coating film formed on a semiconductor substrate such as monocrystal silicon for example. The present invention exhibits its effect specifically in a semiconductor integrated circuit having a large matrix which operates at low speed and a logic circuit for driving it which is required to operate at high speed, such as a liquid crystal display.
Recently, researches on an insulated gate type semiconductor device having a thin film semiconductor layer (also called as an active layer) on an insulating substrate are being conducted and specifically, researches on a thin film insulated gate transistor, i.e. a so-called thin film transistor (TFT), are being actively conducted. They are categorized as an amorphous silicon MFr or a crystal silicon TFT depending on a material and a crystal state of the semiconductor to be used.
Generally, a semiconductor in the amorphous state has a small field mobility, so it cannot be utilized for a TFr which is required to operate at high speed. Then, research and development on the crystal silicon TFT are being conducted in order to fabricate a higher performance circuit in these days.
In those TFTs, a thin film semiconductor region of each individual thin film transistor is isolated and hence, the channel portion has not been grounded like the conventional semiconductor integrated circuit on a semiconductor chip. Due to that, deterioration or failure peculiar to the TFT have occurred sometimes. For instance, with regard to a hot carrier implantation phenomenon, it has been extremely difficult to remove accumulated charge because the channel has been put in the state of floating potential.
Then, a gate insulating film has been thickened or applied voltage has been reduced in order to prevent the deterioration and the like caused by the implantation of carrier. However, operating speed decreases if the gate insulating film is thickened. It has been also difficult to reduce the applied voltage because of the requirement of a device. Because driving voltage of a matrix circuit is determined depending on a liquid crystal material in the monolithic active matrix circuit used for a liquid crystal display in particular, it is difficult to change it arbitrarily.
However, the operating speed of the logic circuit decreases if the gate insulating film is thickened. Then, driving voltage has to be increased to maintain the operating speed, increasing power consumption.
FIG. 11A is a block diagram showing the monolithic active matrix circuit used for a liquid crystal display. In the figure, a column driver 1 and a row driver 2 are provided on a substrate 7 as peripheral driver circuits, pixel circuits (pixels) 4 each comprising a transistor and a capacitor are formed in a matrix area 3 and the matrix area is connected with the peripheral circuits through wires 5 and 6.
Among the TFTs used for the driver circuits, high operating speed is required to the TFT composing the logic circuit such as a shift register and high withstand voltage is required to the TFT used in the pixel circuit. Even in the driver circuits, a part of transistors in a switching circuit (e.g. buffer circuit) is required to have high withstand voltage, rather than high operating speed.
Because the high operating speed and the high withstand voltage are contradictory requirements as described above, it has been difficult to form those transistors on one and the same substrate in one and the same process especially when it is required to reduce the power consumption. Accordingly, it is an object of the present invention to solve such difficult problems.
The present invention is characterized in that a thickness of a gate insulating film in a circuit in which priority is given to high operating speed is changed from that of a gate insulating film in a circuit in which priority is given to high withstand voltage. That is, the former is made to be a circuit which is driven in low voltage and operates at high speed and the latter is made to be a circuit having high withstand voltage by reducing the thickness of the gate insulating film of the former as compared to that of the latter.
In this case, among peripheral circuits, the circuits in which priority is given to high operating speed include logic circuits such as a shift register, a CPU, a memory circuit and a decoder circuit. Further, among peripheral circuits, the circuits in which priority is given to high withstand voltage include a high withstand voltage switching circuit, a buffer circuit and others.
A matrix circuit is also the circuit in which priority is given to high withstand voltage, though it is not the peripheral circuit.
Their difference is distinguished by a variation of voltage applied to the gate electrode in general. That is, the width of variation of voltage applied to the gate electrode is small in the former rather than in the latter.
Then, a semiconductor integrated circuit of a first invention is characterized in that a thickness of at least one gate insulating film of the thin film transistor of the circuit in which priority is given to high operating speed is 80% or less of a thickness of a gate insulating film of the thin film transistor of the circuit in which priority is given to high withstand voltage.
A semiconductor integrated circuit of a second invention is characterized in that at least one layer of another insulating layer is used for at least one gate insulating film of the thin film transistor of the circuit in which priority is given to high withstand voltage in addition to an insulating layer composing at least one gate insulating film of the thin film transistor of the circuit in which priority is given to high operating speed.
A semiconductor integrated circuit of a third invention is characterized in that when at least one gate insulating film of the thin film transistor of the circuit in which priority is given to high operating speed is assumed to be a first insulating layer, at least one gate insulating film of the thin film transistor of the circuit in which priority is given to high withstand voltage is composed of, in addition to the first insulating layer, a second insulating layer formed in a different process from the first insulating layer.
A semiconductor integrated circuit of a fourth invention is characterized in that in the semiconductor integrated circuit having a first thin film transistor and a second thin film transistor each having a gate insulating film whose thickness is different, the thickness of the gate insulating film of the first thin film transistor is 80% or less of the thickness of the gate insulating film of the second thin film transistor and a length of a channel of the first thin film transistor is 80% or less of a length of a channel of the second thin film transistor.
The semiconductor integrated circuit of the fourth invention is also characterized in that the thin film transistor used in the peripheral circuit which is required to operate at high speed is micronized in accordance to scaling law.
Specifically, the present invention is characterized in that the length of the channel in the circuit in which priority is given to high operating speed is changed from that of the channel in the circuit in which priority is given to high withstand voltage. That is, the length of the channel of the former is shortened as compared to that of the latter, or the length of the channel of the latter is prolonged as compared to that of the former, so as to make the former a transistor which is driven in low voltage and which operates at high speed and the latter a transistor of high withstand voltage.
Here, the scaling law to reduce physical dimensions of the TFT or wiring composing it an interlayer film and others in inversely proportional to a certain coefficient. It allows enhancement of performance to be achieved in the same time with highly densified separation of devices.
According to the present invention, electrical characteristics of the peripheral circuit which is required to operate at high speed is improved by micronizing the channel length and the thickness of the gate insulating film in-particular.
The micronization of the channel length may be achieved by modifying a shape of a mask in forming the gate electrode.
In the first through fourth invention described above, it is possible to include a low concentration impurity region that is formed by utilizing a difference of the thickness of the gate insulating films in the thin film transistor of the circuit in which priority is given to high withstand voltage. It allows high withstand voltage characteristics to be enhanced further.
Further, in the third invention described above, the chemical composition of the first insulating layer may be differentiated from that of the second insulating layer. Thereby, it becomes advantageous in fabricating them.
Similarly to that, in the third invention described above, only either one of the first insulating layer or the second insulating layer may be formed by means of thermal oxidation. It is of course possible to form the both by means of the thermal oxidation.
As for a method for fabricating the inventive semiconductor integrated circuit, there are the following inventions. The fifth invention comprises steps of:
1) forming a thin film semiconductor region utilized for a thin film transistor of a circuit in which priority is given to high withstand voltage and a thin film semiconductor region utilized for a thin film transistor of a circuit in which priority is given to high operating speed;
2) forming a first insulating layer covering both of the thin film semiconductor regions;
3) selectively removing the first insulating layer to remove all the first insulating layer covering the thin film semiconductor region composing at least one of the thin film transistor of the circuit in which priority is given to high operating speed by; and
4) forming a second insulating layer covering both of the thin film semiconductor regions.
The sixth invention comprises steps of:
1) forming a thin film semiconductor region utilized for a thin film transistor of a circuit in which priority is given to high withstand voltage and a thin film semiconductor region utilized for a thin film transistor of a circuit in which priority is given to high operating speed;
2) forming a first insulating layer covering both of the thin film semiconductor regions;
3) forming a second insulating layer covering the first insulating layer; and
4) selectively removing the second insulating layer to remove all the first insulating layer covering the thin film semiconductor region composing at least one of the thin film transistor of the circuit in which priority is given to high operating speed.
The seventh invention comprises steps of:
1) forming a thin film semiconductor region utilized for a thin film transistor of a circuit in which priority is given to high withstand voltage and a thin film semiconductor region utilized for a thin film transistor of a circuit in which priority is given to high operating speed;
2) selectively forming a first insulating layer covering both of the thin film semiconductor region except part of the thin film semiconductor region composing at least one of the thin film transistors of at least the circuit in which priority is given to high operating speed; and
3) forming a second insulating layer covering both of the thin film semiconductor regions.
In the fifth through seventh inventions described above, the first insulating layer may be formed by means of thermal oxidation. The second insulating layer may be also formed by means of thermal oxidation as a matter of course.
The fifth through seventh inventions described above may further comprise a step of forming gate electrodes whose width is different owing to shapes of mask of the gate electrodes so that the width of the gate electrode of the second thin film transistor is larger than the width of the gate electrode of the first thin film transistor.
It also comprises a step of forming a channel region having almost the same width with the width of the gate electrode under the gate electrode in a step of doping to the active layer.
While the length of the channel of the first thin film transistor has been set to be 80% or less of the length of the channel of the second thin film transistor, it has been found that the electrical characteristics such as operating speed improves when the ratio of the length of the channel of the first thin film transistor to that of the second thin film transistor is set preferably at 0.1 to 0.5.
Therefore, the ratio of the width of the gate electrode of the first thin film transistor to the width of the gate electrode of the second thin film transistor has been set within a range of 0.1 to 0.5.
The electrical characteristics such as operating speed improves further when the thickness of the gate insulating film of the first thin film transistor and the second thin film transistor is adjusted in accordance to this ratio.
Thereby, the thickness of the gate insulating film or the channel length may be changed in the circuit which is required to operate at high speed (e.g. a logic circuit in a monolithic active matrix circuit) and the circuit which is required to have high withstand voltage (a matrix circuit in the monolithic active matrix circuit). As a result, as for the monolithic active matrix circuit, the logic circuit which is driven in low voltage and operates at high speed and the high withstand voltage matrix circuit may be obtained on one and the same substrate, which is the purpose of the present invention. It is noted that as disclosed in, for example, Japanese Patent Laid Open No. Hei. 7-135323, the disclosure of which is herein incorporated by reference, the present invention is applicable to a semiconductor integrated circuit in which various memories and arithmetic devices are provided as logic circuits on one and the same substrate (see FIG. 11B). In FIG. 11B, a correction memory 8, a memory 9, an input port 10, a CPU 11, and an XY branch 12 are formed on a substrate 7 as well as a column decoder/driver 1, a row decoder/driver 2, and an active matrix 3. The present invention will be explained below in detail with reference to preferred embodiments.